As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of semiconductor devices. As one example, with progressively finer design rules, a problem has arisen due to capacitance between adjacent metal layers (i.e. interlayer capacitance). That is, as devices shrink in size, adjacent layers are spaced more closely together. Such a condition results in a deleterious increase in interlayer capacitance which adversely affects operation of finer design rule-based semiconductor devices. A similar problem exists due to the reduced distance between adjacent metal lines. Specifically, under some circumstances, unwanted effects such as cross-talk and various other RC (resistance/capacitance) effects between closely spaced metal lines negatively affect the operation of the semiconductor devices.
It is well known that the dielectric constant for a conventional interlayer dielectric material such as, for example, CVD-deposited silicon dioxide is around 3.9. However, according to the SIA (Semiconductor Industry Association) roadmap, by the year 2005 ultra-low dielectric constant materials (i.e. materials with a dielectric constant of 2.0 or less) will be required for use in 100 nanometer generation integrated circuits. Therefore, it is increasingly important to reduce the dielectric constant of an interlayer and/or intermetal insulating material.
It is generally agreed that only porous materials can achieve the desired reduced dielectric constants (i.e. dielectric constant of less than 2.0). One conventional method for creating a porous dielectric material is to positively form voids within the material. In one prior art approach, small particles within the dielectric are subjected to an etching process. However, such a prior art approach is not particularly cost effective, is not time effective, and does not readily produce desired results.
Furthermore, in order to achieve widespread acceptance, and to ensure affordability, any method of forming a low dielectric constant nanoporous material, which overcomes the above-listed drawbacks, should be compatible with existing semiconductor fabrication processes.
Thus, a need exists for a method for forming a nanoporous material for reducing interlayer capacitance and reducing RC effects between neighboring metal lines. Yet another need exists for a method for forming a nanoporous material which meets the above need and which does not require etching of small particles. Still another need exists for a method for forming a nanoporous material wherein the method meets all of the above-listed needs and wherein the method is compatible with existing semiconductor fabrication processes.